This invention generally relates to digital data processing systems. More specifically it relates to a processor for use in such data processing systems.
A digital data processing system comprises three basic elements: namely, a memory element, an input-output element and a processor element. The memory element stores information in addressable storage locations. This information includes data and instructions for processing the data. The processor element transfers information from the memory element. It interprets the incoming information as either data or an instruction. An instruction includes an operation code that specifies, in coded form, the operation to be performed by the processor. An instruction may also include information that specifies one or more operands. The information that specifies an operand is called an operand specifier.
In a simple digital data processing system, the processor operates in response to instructions that have a fixed format and a fixed length. More specifically, in one such digital data processing system the instructions are classified as memory reference instructions and operation instructions, the latter also being known as "microinstructions". Each memory reference instruction requires an operand specifier to specify the address of the location to which the instruction refers. Therefore, the instruction comprises an operation code and an operand specifier. In this system the memory is divided into pages. The most significant bit in the operand address controls whether the processor interprets the operand address as referring to the page containing the instruction or to a reference page. The microinstructions contain no operand specifiers, operands being implicitly addressed by the instructions.
These simple instructions of fixed length and fixed format provide very elementary functions. It is, therefore, difficult to write a program which will solve a complex problem, primarily because a very large number of instructions are required.
More recent processors perform more complex functions in response to single instructions. Some of these processors still involve fixed format instructions, but, to a limited degree, they are capable of responding to instructions of variable length. For example, one such processor allows variable length instructions that include an initial byte (a fixed group of binary digits or bits) which the processor interprets as an operation code. This operation code then is followed in the instruction by successive bytes that designate predetermined registers in the central processor. However, even in this approach, the instruction format is still fixed.
Another type of central processor that provides a type of variable length instruction is used in a PDP11 data processing system and is disclosed in the foregoing U.S. Pat. No. 3,654,741. In that processor an instruction may include up to two operand specifiers. Moreover, the instruction and all the information for specifying the two operands can require from two through six consecutive byte positions in the program. An operator group of instructions, for example, contains no operand specifiers, but the instruction is stored as one word comprising two bytes. Other instructions contain two operand addresses. Both operands may be specified within the instruction word. If, however, both operand addresses in an instruction specify an addressing mode that identifies the program counter, six consecutive byte positions in the program are required to define the instruction completely. With this approach, however, the length of the operand is implicitly specified because the operation code defines the number of operands and other bits in the instruction itself define the total length of the operand specifiers.
Thus, even in these central processors, it is often necessary to process two or more instructions in order to perform a specific function. For example, if a programmer wishes to add two numbers and store the sum in a third memory location without disturbing the locations that store the addends, he must use an instruction to copy one addend into the third location and then an instruction for adding the other addend with the contents of the third location. The constraints imposed by these instructions can lead to programming errors and processor inefficiency.
Therefore, it is an object of this invention to provide a processor for a digital data processing system that is adapted to process a flexible set of instructions.
Another object of this invention is to provide a processor for use in a digital data processing system that can process an instruction having any length.
Another object of this invention is to provide a processor for a digital data processing system that processes variable length instructions, thereby to enable a programmer to write more compact programs.
Still another object of this invention is to provide a processor for a digital data processing system in which the instructions processed by the central processor can easily be extended to include any number of operand specifiers.
Yet another object of this invention is to provide a central processor which can process an instruction with a variable-length operation code.